This invention relates to an integrated circuit comprising a CPU for downloading a program via serial communication and executing the program and to an information processing apparatus, such as a mobile telephone and a computer, having the above-mentioned integrated circuit.
In order to achieve or add a particular function in an existing integrated circuit, such as an LSI containing a CPU, a program to be executed by the CPU to achieve or add the particular function is stored in a mask ROM.
Recently, however, following an increase in complexity of a system and an increase in scale of the program, there is an increasing risk of occurrence of defects or troubles after the program is stored in the mask ROM.
In view of the above, in the integrated circuit of the type, it is proposed to store the program in a rewritable nonvolatile memory (flash memory). Upon occurrence of defects or troubles, the program is updated by rewriting.
However, since the nonvolatile memory is generally an external memory, there arises a problem that a mounting area is increased and a production cost is elevated.
Taking the above into consideration, it is proposed that the integrated circuit of the type is provided with an internal RAM. The program downloaded from a superior or master integrated circuit is stored in the RAM and then executed by the CPU.
Hereinafter, description will be made of an existing information processing apparatus having an integrated circuit in which a program downloaded via serial communication is stored in a RAM and then executed by a CPU.
Referring to FIG. 1, the existing information processing apparatus comprises a master device 8 and a slave device 9.
The master device 8 is an LSI comprising a CPU 81 and a synchronous serial interface (SSI) 82 as a master interface.
The slave device 9 is an LSI comprising a CPU 91 adapted to download a program from the master device 8 via serial communication and to execute the program. The CPU 91 is connected to a ROM 93 and a RAM 94 through a bus control circuit 95. The ROM 93 stores a program for executing a downloading operation. The RAM 94 serves to store the program downloaded from the master device 8 to be executed by the CPU 91, together with work data.
The slave device 9 further comprises a synchronous serial interface (SSI) 92 as a slave interface for carrying out communication with the master device 8 through a communication path/control signal line 10 and for downloading a program from the master device 8.
Next referring to FIG. 2, description will be made of the structure of the synchronous serial interface 92 in the slave device 9.
Referring to FIG. 2, the synchronous serial interface 92 in the existing information processing apparatus comprises a bus interface circuit 921 connected to the CPU 91 through the bus control circuit 95, a transmission FIFO 922 and a transmission circuit 923 arranged on a transmitting side, a reception FIFO 924 and a reception circuit or receiver circuit 925 arranged on a receiving side, and a timing control circuit 926 for carrying out control related to communication processing.
In case where data from the CPU 91 is transmitted to the master device 8, the timing control circuit 926 transmits the data through the transmission FIFO 922 and the transmission circuit or transmitter circuit 923. On the other hand, in case where data from the master device 8 is received, the timing control circuit 926 makes the reception FIFO 924 store the data transmitted from the master device 8 and received by the reception circuit 925. The data stored in the reception FIFO 924 is read out by the CPU 91 through the bus interface circuit 921.
Hereinafter, operation of the existing information processing apparatus will be described. Herein, description will be made of the case where the slave device 9 downloads a program from the master device 8 via four-wire synchronous serial communication using four signal lines for a chip select (CS), clock (CLK), output data or serial-data-out (SDO), and input data or serial-data-in (SDI).
Referring to FIGS. 3 and 4, operation of the master device 8 will be described. In FIGS. 3 and 4, CS, CLK, and SDO represent the chip select, the clock, and the output data produced by the master device 8, respectively. In FIG. 4, SDI represents the input data supplied to the master device 8.
Referring to FIGS. 3 and 4, the output data (SDO) from the master device 8 has a format including an address/control field (hereinafter referred to as an address field, the field having the length of 8 bits in FIGS. 3 and 4) and a data field (the field having the length of 8 bits in FIGS. 3 and 4) following the address field. FIG. 3 shows the case where data is transferred from the master device 8 to the slave device 9. FIG. 4 shows the case where a data transfer request is sent from the slave device 9 to the master device 8. Although not illustrated in the figure, the output data (SDO) from the slave device 9 has a similar format containing an address field and a data field following the address field.
When data is received by the reception circuit 925, the slave device 9 judges, with reference to setting of the address field of the data, whether incoming data from the master device 8 is being received or outgoing data is being transmitted to the master device 8.
Specifically, in the slave device 9, the reception circuit 925 receives the data in the address field and transmits it to the timing control circuit 926. When it is judged with reference to the setting of the address field data that the outgoing data is being transmitted to the master device 8, the timing control circuit 926 read the data from the transmission FIFO 922 into the data field and transmits the data through the transmission circuit 923. On the other hand, if it is judged that the incoming data from the master device 8 is being received, the data in the data field received by the reception circuit 925 is stored in the reception FIFO 924 as shown in FIG. 5. In FIG. 5, CS, CLK, and SDI represents a chip select, clock, and input data or serial-data-in supplied from the master device 8 to the slave device 9, respectively, and Reception FIFO represents the data stored in the reception FIFO 924 in the slave device 9.
The above-mentioned technique of transferring data, such as a program, between the master and the slave devices is disclosed, for example, in Japanese PatentApplication Publications (JP-A) Nos. H07-312627, 2001-134543, and 2003-029809.
However, the existing information processing apparatus is disadvantageous in the following respects. In case where the program is increased in size, it takes a very long time for a lower or slave integrated circuit to download the program by the use of a typical interface such as UART (Universal Asynchronous Receiver Transmitter). In order to download the program at a high speed, the lower integrated circuit must have a specific or exclusive-use high-speed interface.
In the existing information processing apparatus, only one byte of significant data (program) can be transferred in one-chip transfer as shown in FIG. 5, resulting in decrease of the throughput. Therefore, much longer time is required to download the program.